1. Field of the Invention
The present invention relates generally to static memory testing, and more specifically to an improved method and structure for performing long write tests on static memories.
2. Description of the Prior Art
Writing to a memory cell or cells of static memories, such as static random access memories (SRAMs), multiple port memories, and First In First Out (FIFO) memories, can sometimes affect adjacent memory cells on the same column that share a bitline. These memory cells should not be affected if their wordlines are off; however, leakage from a memory cell node to a bitline may be enough to overcome the pull-up resistance of the memory cell, causing the data of the memory cell to be corrupted. This problem is exacerbated by a long write cycle, because there is greater opportunity for such leakage to occur. Therefore, memory cell node to bitline leakage and subsequent corruption of memory cells is often a concern during long write testing of a static memory.
Long write testing is conducted after writing a test data pattern to selected memory cells of a static memory. The long write test problem occurs when writing to memory cells along a column and inadvertently affecting non-selected memory cells, whose wordlines are off. The non-selected memory cells that are affected have leakage problems from a memory cell node to a bitline that cause them to erroneously change state. The write cycle during a long write test is typically quite long, thereby providing time for the leakage problem to occur. To screen for leakage problems, test modes have been proposed which, after the wordlines of all memory cells are turned off, pull down bitline true or bitline complement of the entire memory array or a subset of the memory array in order to "disturb" the memory cells. The memory cells are then read following the disturb condition to check for errors in the states of individual memory cells.
However, two issues must be considered before adopting such a test mode. First, the data state of a memory cell and adjacent memory cells, on all sides of the memory cell, can be critical in determining whether the memory cell has a propensity to be disturbed during long write testing. For instance, memory cells tend to fail on either the bitline true or the bitline complement side of the cell, because only one side of a memory cell usually leaks. Thus, a memory cell may be more likely to fail if it has a 0 or a 1 stored in it. Additionally, adjacent memory cells frequently share common connections to power supplies. Therefore, the state of data stored in a memory cell, the state of data stored in adjacent memory cells, and the fact that memory cells may share common connections to power supplies are all factors which can greatly affect the memory cell's sensitivity to long write testing.
Second, when pulling down multiple bitlines of a memory cell, it is necessary to first turn off the bitlines in order to decrease power consumption. Incorporating the necessary bitline control to turn off appropriate bitline loads and pull bitlines to ground during the disturb for the various test data patterns to which a static memory is typically subjected necessarily introduces complicated circuitry to perform the requisite independent bitline load control function. Such complicated circuitry takes up valuable space within the static memory. A possible solution to these competing interests is to pull low the bitline true for all memory cells being tested and to leave the bitline complement high for all memory cells being tested; or, some other simple pattern may be used. However, such schemes have limited practical use, because they do not address the great number of different test data patterns typically used to test static memories.